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Chrontel
CH7017A
Brief Datasheet
CH7017 TV Encoder / LVDS Transmitter
Features
TV-Out: * VGA to TV conversion supporting up to 1024x768 pixels. * MacrovisionTM 7.1.L1 copy protection support. * Two variable-voltage digital input ports. * Simultaneous LVDS and TV output. * True scale rendering engine supporting under-scan in all TV output resolutions. * Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering. * Support for NTSC and PAL TV formats. * Outputs CVBS, S-Video, RGB and YPrPb. * Support for SCART output. * TV / Monitor connection detect. * Output video switch for easy wiring to connectors. LVDS-Out: * Single / Dual LVDS transmitter. * Dual LVDS supporting pixel rates up to 330Mpixels/sec when both 12-bit input ports are ganged together. * Panel fitting scaler - up scale to 1600x1200 pixels. * LVDS low jitter PLL accepting EMI reduction input. * LVDS 18-bit and 24-bit outputs. * 2D dither engine. * Panel protection and Power-Down sequencing. * Programmable power management. * * * * * * Support for second CRT DAC bypass mode. Four 10-bit video DAC outputs. Fully programmable through serial port. Complete Windows and DOS driver support. Variable voltage interface to graphics device. 128-pin LQFP package.
1.0 General Description
The CH7017 is a Display Controller device that accepts two digital graphics input data streams. One data stream outputs through an LVDS transmitter to a LCD panel, while the other data stream is encoded for NTSC or PAL TV and outputs through four 10-bit high-speed DACs. The TV encoder device encodes a graphics signal up to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS transmitter operates at pixel speeds up to 165MHz per link, supporting 1600x1200 panels at 60Hz refresh rate. The device can also accept one graphics data stream over two 12-bit wide variable voltage ports which support nine different data formats including RGB and YCrCb (RGB must be used for LVDS output). A maximum of 330M pixels per second can be output through dual LVDS links. The TV-Out processor will perform non-interlaced to interlaced conversion with scaling, flicker filtering, and encoding into any of the NTSC or PAL video standards. The scaler and flicker filter are adaptive and programmable for superior text display. Eight graphics resolutions are supported up to 1024 by 768 pixels with full vertical and horizontal under-scan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Anti-copy protection support is provided by MacrovisionTM technology. In addition to TV encoder modes, bypass modes are included which allow the TV DACs to be used as a second CRT DAC. The LVDS transmitter includes a panel fitting up-scaler and a programmable dither function for the support of 18-bit panels. Data is encoded into commonly used formats, including those detailed in the OpenLDI and the SPWG specifications. Serialized data outputs on three to eight differential channels. Patent number 5,781,241 Patent number 5,914,753
TV PLL TV Timing Data Mux / Format Deflicker / Text Enhancement / Scaling / Scan Conversion / TV Encode Four 10-bit DAC's Analog Video Switch
2 4 4
XCLK1,XCLK1* H1,V1, DE1 FLD/STL1 D1[11:0]
2 3
12
Clock, Data, Sync Latch & Demux
P-OUT BCO/VSYNC C/HSYNC DACA[3:0] DACB[3:0]
XCLK2,XCLK2* H2,V2, DE2 FLD/STL2 D2[11:0]
2 3
12
Clock, Data, Sync Latch & Demux
LVDS PLL Up-Scaler / Dither LVDS Encode / Serialize LVDS Transmit
8 2 2 8 2
LDC[3:0],LDC*[3:0] LL1C,LL1C* ENAVDD, ENABKL LDC[7:4],LDC*[7:4] LL2C, LL2C*
VREF1 Serial Port Control and Misc. Functions XTAL
2
XI/FIN,XO
SPC
SPD
VOUT
RESET*
HOUT
HPD
AS
HPINT*
DD1,DD2
DC1,DC2
Figure 1: CH7017 Functional Block Diagram 209-0000-015 Rev. 1.4, 2/06/2003 1
SDD,SDC
GPIO[5:0]
VREF2
VIN
HIN
CHRONTEL
2.0 Pin Assignment
2.1 Package Diagram
ENABKL ENAVDD GPIO[3] GPIO[2] GPIO[1] GPIO[0] HPINT* HPD VOUT HOUT V5V DC2 DD2 DC1 DD1 SDC SDD VREF2 VIN HIN SPC SPD AS FLD/STL2 DE2 DVDD
CH7017A
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
LPLL_VDD LPLLCAP LPLL_GND LGND LL2C LL2C* LVDD LDC7 LDC7* LGND LDC6 LDC6* LVDD LDC5 LDC5* LGND LDC4 LDC4* LVDD LVDD LDC3 LDC3* LGND LL1C LL1C* LVDD LDC2 LDC2* LGND LDC1 LDC1* LVDD LDC0 LDC0* LGND VSWING DAC_VDD ISET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Chrontel CH7017
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
V2 H2 DGND D2[11] D2[10] D2[9] D2[8] D2[7] D2[6] XCLK2 DGND XCLK2* D2[5] D2[4] D2[3] D2[2] D2[1] D2[0] DVDD DVDD D1[11] D1[10] D1[9] D1[8] D1[7] D1[6] XCLK1 DGND XCLK1* D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] DGND H1 V1
2
DAC_GND N/C CVBS (DACA3) Y/G (DACB1) Y/G (DACA1) Pr/R (DACB2) C/R (DACA2) Pb/B (DACB0) CVBS/B (DACA0) DAC_GND C/HSYNC BCO/VSYNC TVPLL_GND XI / FIN XO TVPLL_VCC TVPLL_VDD GPIO[4] GPIO[5] RESET* P-OUT VDDV VREF1 FLD/STL1 DE1 DVDD
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Figure 2: CH7017 128 Pin LQFP Package (Top View) 209-0000-015 Rev. 1.4,
2/06/2003
CHRONTEL
2.2 Pin Description
# of Pins Type 2 In/Out Symbol H1, H2
CH7017A
Table 1: Pin Description
Pin # 66, 101 Description Horizontal Sync Input / Output When the SYO control bit is low, these pins accept a horizontal sync inputs for use with the input data. The amplitude will range from 0 to VDDV. VREF1 is the threshold level for these inputs. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a 64-pixels wide horizontal sync pulse from one of these pins. The output is driven from the DVDD supply, and it is valid ONLY when TV-Out is in operation. Vertical Sync Input / Output When the SYO control bit is low, these pins accept a vertical sync inputs for use with the input data. The amplitude will range from 0 to VDDV. VREF1 is the threshold level for these inputs. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a 1-line wide vertical sync pulse from one of these pins. The output is driven from the DVDD supply, and it is valid ONLY when TV-Out is in operation. Data Enable These pins accept a data enable signal that is high when active video data is input to the device, and remains low during all other times. The amplitude will range from 0 to VDDV. VREF1 is the threshold level for these inputs. The TV-Out function uses H and V sync signals and values in the SAV Register as reference to active video. TV Field / Flat Panel Stall Signal These outputs can be programmed to be either a TV Field output from the TV encoder, or a Stall output from the flat panel Up-scaler. These outputs are tri-stated upon power up. Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port. It can operate with input levels from VDDV to DVDD. Outputs are driven from 0 to VREF2. Serial Port Clock Input This pin functions as the clock input of the serial port. It can operate with input levels from VDDV to DVDD. Address Select (Internal Pull-up) This pin determines the device address of the serial port. Low-Voltage DDC Serial Data Low-voltage serial data for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. Low-Voltage DDC Serial Clock Low-voltage serial clock for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. DDC Serial Data Serial data for DDC. (0V to 5V) Reference Voltage 2 Used to generate the output supply level for the SPD port. This pin should be tied externally to the maximum voltage seen by the ports. (1.5V to 3.3V). DDC Serial Clock Clock for DDC. (0V to 5V) General Purpose Input / Output [5:0] These pins provide general purpose I/O and are controlled via the serial port. (3.3V). See description of GPIO Controls for I/O configuration. Panel Power Enable Enable panel VDD. (3.3V) Back Light Enable Enable Back-Light of LCD Panel. (3.3V)
65, 102
2
In/Out
V1, V2
63, 104
2
In
DE1, DE2
62, 105
2
Out
FLD/STL1, FLD/STL2 SPD
107
1
In/Out
108 106 112 113 114, 116 111 115, 117
1 1 1 1 2 1 2
In In In/Out In/Out In/Out In In/Out In/Out Out Out
SPC AS SDD SDC DD1, DD2 VREF2 DC1, DC2 GPIO[5:0] ENAVDD ENABLK
123-126, 56, 6 57 127 128 1 1
209-0000-015
Rev. 1.4,
2/06/2003
3
CHRONTEL
Table 1: Pin Description (Continued)
Pin # 121 # of Pins Type 1 In Symbol HPD
CH7017A
Description Hot Plug Detect (Internal Pull-down) This input pin determines whether a display device is connected to the VGA connector. When terminated, the display device is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the HPINT* pin pulling low. Hot Plug Interrupt Output This pin provides an open drain output, which pulls low when a termination change has been detected on the HPD input. LVDS Voltage Swing Control This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor should be connected between this pin and LGND (pin 35) using short and wide traces. Reset * Input (Internal Pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port. LVDS PLL Capacitor This pin allows coupling of any signal to the on-chip loop filter capacitor. Positive LVDS differential Clock2 & Clock1 Negative LVDS differential Clock2 & Clock1 Positive LVDS differential data[7:4] Negative LVDS differential data[7:4] Positive LVDS differential data[3:0] Negative LVDS differential data [3:0] Current Set Resistor Input This pin sets the DAC current. A 140-ohm resistor should be connected between this pin and DAC_GND (pin 39) using short and wide traces.
122 36
1 1
Out In
HPINT* VSWING
58 2 5, 24 6, 25 8, 11, 14, 17 9, 12, 15, 18 21, 27, 30, 33 22, 28, 31, 34 38 41
1 1 2 2 4 4 4 4 1 1
In Analog Out Out Out Out Out Out Analog Out
RESET* LPLLCAP LL2C, LL1C LL2C*, LL1C* LDC[7:4] LDC[7:4]* LDC[3:0] LDC[3:0]* ISET
CVBS
(DACA3)
Composite Video
This pin outputs a composite video signal capable of driving a 75 ohm doubly terminated load. During bypass modes this output is valid only if the data format is compatible with one of the TV-Out display modes.
42
1
Out
Y/G
(DACB1)
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be the luminance component of YPrPb or green (for VGA bypass)
43
1
Out
Y/G
(DACA1)
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be s-video luminance or green (for SCART type 1 connections) or the luminance component of YPrPb or green (for VGA bypass)
44
1
Out
Pr/R
(DACB2)
Pr / Red Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be the Pr component of YPrPb or red (for VGA bypass)
45
1
Out
C/R/Pr
(DACA2)
Chroma / Red Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be s-video chrominance or red (for SCART type 1 connections) or the Pr component of YPrPb or red (for VGA bypass)
46
1
Out
Pb/B
(DACB0)
Pb / Blue Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to the Pb component of YPrPb or blue (for VGA bypass).
47
1
Out
CVBS/B/Pb
(DACA0)
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be composite video or blue (for SCART type 1 connections) or the Pb component of YPrPb or blue (for VGA bypass).
120
1
Out
VOUT
V-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V.
4
209-0000-015
Rev. 1.4,
2/06/2003
CHRONTEL
Table 1: Pin Description (Continued)
Pin # 110 # of Pins Type 1 In Symbol VIN
CH7017A
Description V-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2. H-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V. H-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2 Composite / Horizontal Sync This pin provides composite sync in TV modes and horizontal sync in bypass RGB mode. This pin is driven by the DVDD supply. Buffered Clock Outputs / Vertical Sync This output pin provides buffered crystal oscillator clock output or VSYNC output in bypass RGB mode. This pin is driven by the DVDD supply. Crystal Input / External Reference Input A parallel resonant 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XO. However, an external CMOS compatible clock can drive the XI/FIN input. Crystal Output A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XI / FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open. Pixel Clock Output This pin provides a pixel clock signal to the VGA controller, which can be used as a reference frequency. The output is selectable between 1X and 2X of the pixel clock frequency. The output driver is driven from the VDDV supply (pin 60). This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum. Reference Voltage Input 1 The VREF1 pin inputs a reference voltage of VDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync and clock inputs. Data1[11] through Data1[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV. VREF1 is the threshold level. External Clock Inputs These inputs form a differential clock signal input to the device for use with the H1, V1 and D1[11:0] data. If differential clocks are not available, the XCLK1* input should be connected to VREF1. The clock polarity can be selected by the MCP1 control bit. Data2[11] through Data2[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV. VREF1 is the threshold level. External Clock Inputs These inputs form a differential clock signal input to the device for use with the H2, V2 and D2[11:0] data. If differential clocks are not available, the XCLK2* input should be connected to VREF1. The clock polarity can be selected by the MCP2 control bit. 5V supply for H/VOUT (5V) Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) TV PLL Supply Voltage (3.3V) TV PLL Supply Voltage (3.3V) TV PLL Ground DAC Supply Voltage (3.3V)
119 109
1 1
Out In
HOUT HIN
49 50
1 1
Out Out
C/HSYNC BCO/VSYNC
52
1
In
XI / FIN
53
1
Out
XO
59
1
Out
P-Out
61
1
In
VREF1
68-73, 77-82
12
In
D1[11:0]
76, 74
2
In
XCLK1, XCLK1*
85-90, 94-99
12
In
D2[11:0]
93, 91
2
In
XCLK2, XCLK2*
118 64, 83, 84, 103 67, 75, 92, 100 60 55 54 51 37
1 4 4 1 2 1 1 1
Power Power Power Power Power Power Power Power
V5V DVDD DGND VDDV TVPLL_VDD TVPLL_VCC TVPLL_GND DAC_VDD
209-0000-015
Rev. 1.4,
2/06/2003
5
CHRONTEL
Table 1: Pin Description (Continued)
Pin # 39, 48 7, 13, 19, 20, 26, 32 4, 10, 16, 23, 29, 35 1 3 # of Pins Type 1 Power 6 Power 6 1 1 Power Power Power Symbol DAC_GND LVDD LGND LPLL_VDD LPLL_GND Description DAC Ground LVDS Supply Voltage (3.3V) LVDS Ground LVDS PLL Supply Voltage (3.3V) LVDS PLL Ground
CH7017A
6
209-0000-015
Rev. 1.4,
2/06/2003
CHRONTEL
3.0 Package Dimensions
128 1
CH7017A
A1 B1
103 102
I
A2 B2
38 39 64
65
H J
C
D
F G
E
LEAD
.004
Table of Dimensions
No. of Leads 128 (14X20)
Millimeters MIN MAX 16 22 14 20 0.50 0.17 0.27 1.35 1.45 0.05 0.15 1.00 0.45 0.75 0.09 0.20 0 7
SYMBOL
A1 A2 B1 B2 C D E F G H I J
209-0000-015
Rev. 1.4,
2/06/2003
7
CHRONTEL
Disclaimer
CH7017A
This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number CH7017A-T Package Type LQFP Number of Pins 128 Voltage Supply 3.3V
Chrontel
2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
2002 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.
8
209-0000-015
Rev. 1.4,
2/06/2003

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